Monroe 950 Technology
Most ICs data coded from 1970, quite late in the life of DTL. PCBs are clearly marked “Canon Inc”.
Architecture, Memory & Speed
- 16 displayed digits, 1 sign lamp
- Digit encoding and processing scheme remains to be determined but the presence of the “minus zero” quirk suggests that numbers are represented as one’s complement and are processed digit-serially. This architecture would be in keeping with the serial nature of delay line memory.
- Memory is wire delay line
- ??kHz master clock, ??mS cycle times
General construction is in keeping with early-generation values using a substantial chassis with plenty of brackets, supports and fastenings. The PCBs are mounted in plastic carriers which form card guides and provide spacing and support between each board. There is a PCB backplane which seems to have been used in a series of Canon machines, in this machine slots 5 and 6 are empty and unused.
The logic is contained on five double sided PCBs. One board also mounts the nixie tube display while another mounts the delay line memory module. The boards are neatly laid out with some signal names etched into the traces. Most of the logic is implemented with DTL chips, TI’s SN 39xx and 45xx series. There is a small amount of discrete diode logic and just a few transistors in the logic circuits.
The power supply is transformer based with series pass regulation of logic supplies.