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Wang Calculator Wire Braid ROMs

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Microcode ROM

ROM memory became an essential part of calculator architecture with the advent of microcoded architecture. First-generation machines such as the LOCIs and Wang 300 series implemented all functionality with bulk electronic logic, the designers providing specific circuits for each calculator operation. As more ambitious machines were contemplated this approach became a severe constraint. Advanced functions required increasing amounts of complex logic which was challenging to design, required more cabinet space and power, and increased the cost of the machine.

Microcoding overcame these limits by recognising that a simple logic engine could be programmed to perform very complex operations (Universal Turing Machine principle). Calculators with increasing capability could be built from simple logic engines by providing a sophisticated microcode program to drive the logic engine. Complexity moved from hardware to software, hardware size and cost was kept under control and the basic electronic design became longer-lived because functional improvements could be made by altering the microcode program. Microcoding marked the beginning of the next generation of calculators - the Wang 700s and HP9100s.

The limiting factor for the introduction of microcoded architectures in desktop calculators was the availability of ROM with size and cost compatible with desktop calculators. Silicon chip ROMs had become available in the late 1960s, but seemingly too late for the Wang 700 and HP 9100 designers. The Wang 700 requirement was to store 1792 43-bit microcode words (approx 9.6k bytes) and the designers turned to magnetic core technology, something very familiar to Wang.

Wire Braid ROM

The Wang 700 uses a Wire-Braid ROM where each of the 43 output bits is represented by a ferrite ring which acts as a current sense transformer. ROM addresses are decoded into a set of address wires, one wire for each address. The ROM is constructed by threading each address wire among the bit rings, passing through a ring to encode a ‘1’ and beside a ring to encode a ‘0’. To read an address the relevant wire is selected and a current pulse is applied. Only bit rings encoded as ‘1’ produce a pulse in the current transformer sense winding and the set of pulses that arise from one address wire are captured as the output word from that address. See the Wire Braid ROM Patent in the Data section for more information, including means to handle the cross-talk that occurred in the tightly bundled address wires. Wire Braid ROM is closely related to Core Rope ROM, notably used in the Apollo Guidance Computers and also used in a section of the logic engine in the HP 9100 calculator.

The bit rings should be small to maximise pulse coupling but since any ring could potentially have all 1792 wires passing within it, this requires that the wires be very fine. Small diameter wires are difficult to handle and a balance must be struck between bit ring and wire size. Address wires are on average 75cm long, so a 1792 address ROM contains around 1400m of wire which must be threaded with absolute accuracy and without breaks. Wang invented and patented (see Data section) a machine to thread the address wires but the ROMs still required further complex assembly with thousands of diodes to install and a final adjustment by hand where component values were trimmed for optimal performance.

Wang Wire Braid ROM

The Wang Wire-Braid ROMs are 43 x 30 x 4cm and can store a maximum of 2048 x 44 bits = 11.3k bytes in a volume of 5160cm3.

The investment of resources and skill required to develop, manufacture and maintain this technology indicates how severe the problem of desktop scale ROM storage was in the middle 1960s. It’s also interesting to note how short-lived this technology was. Wire Braid ROMs were introduced in 1969 for the Wang 700 series and remained the choice in 1972 for the first Wang 600 machines. By 1974 the 600 series had adopted IC MOS ROM where the same amount of data could be stored in 11 4-bit ROMs that occupied just 50 cm3, less than 1% of the volume of the wire braid ROM.

ROM Construction

Wang Wire Braid ROM

The ‘back’ of the ROM PCB has a striking array of diodes, one per ROM address, so a maximum of 2048 diodes with one address wire connected to each diode. The column decoder ICs are in a line across the top while the transistor switches for each bundle of address wires are arranged down the side.

The diode matrix is daunting at first sight but is laid out very logically, with addresses incrementing both down and across the board. It’s not difficult to identify the bundle termination and the specific diode for any particular ROM address, allowing the integrity of any ROM wire and its diode to be tested.

Wang Wire Braid ROM

The ‘front’ or wire side of the ROM is more intimidating and great care is required just to remove the plastic cover. The data wires are very fine and removing spider silk was sufficient to displace and tug on many wires.

64 wires are formed into 32 bundles that attach to transistor drivers at the side of the board. The bundles pass up to the blocks of pulse transformers, each white square can contain 4 transformers for a total of 44 bits of data per address. After threading its data-specific path through the transformers the wire takes a U-turn, is routed to its correct column and then passes down to reach its individual diode. A typical wire is 75cm long and 2048 addresses require 1536m of wire, just under a mile.

Wang invented and patented a machine to thread the wires. This was necessary considering that absolute accuracy was required as well as sufficient speed whan making such a complex item. The patent with further interesting details is in the Data section. It’s impressive to see that this machine was possible with 1960s technology.

Wang Wire Braid ROM

ROM Details and Repairs

The ROM is an ambitious design and a very impressive piece of construction, also very pretty to look at.

There are accounts of the ROMs being repaired and the ROMs shown here have clear evidence of broken wires that have been glued to the plastic guides. Presumably it was too difficult to remove such wires and better to thread a replacement. It seems most likely that this was done during construction if a wire broke during initial threading. In this situation the ROM would have been open for construction and there would have been fewer wires interfering with access to the problem.

Some of DoPECCs ROMs have open-circuit data wires but after very careful consideration it seems entirely impractical to repair or replace these wires. The affected wires are buried within dense bundles and/or are covered with layers of other wires. Attempts to solder replacement wires would almost certainly damage many others. It would be necessary to thread replacements into the transformer rings and this would require opening the transformer blocks, with the risk that other wires may spring out and become damaged or lose their place and therefore their data value.

With these factors in mind, no attempts will be made to repair faulty ROM wires. The ROM emulator has been designed to replace the ROM and has other advantages including the ability to run diagnostic microcode if faults occur.