Matching the Emulator to Wang 700 Timing
The Wang 700 was not functional with its original ROM. Fault-finding a microcode based machine poses a circular question - is the fault in the microcode ROM or the execution logic? One way to resolve this is to provide known-good microcode using the DoPECC ROM Emulator. If this fails then the Emulator can provide diagnostic microcode that can help to test and isolate hardware faults.
The DoPECC ROM Emulator had not been used on a Wang 700 series and past experience with its use on a 600 machine had shown the importance of understanding and emulating the actual machine timings, rather than depending on analysis of schematics.
Wang 700 ROM Timing
Monitoring the Wang 700 during a ROM read cycle showed that the CPR pulse to activate the ROM was around 400 nS long. This is the only signal that drives the 700 ROM and a number of important events occur during its activity:
- Spurious ROM outputs can be generated in the first part of CPR and these must be ignored.
- The ROM data latches must be cleared in preparation for the new ROM data, this is done by the P2 signal and it can be seen that P2 overlaps the latter part of CPR.
- The first use of the new ROM data is in P4, when the A, B and Z bus addresses are latched by P4.
This suggests that the Emulator should be set up such that:
- ROM data not available during CPR,
- ROM outputs must be logical zeros (high) during P2 so that the S-R ROM data latches in the logic engine can be reliably reset by P2,
- ROM data must become available after P2 and be stable by the start of P4 when it is first latched,
- ROM data can remain active for the remainder of the machine cycle because
- All ROM data latches hold their state until cleared by next P2
- ROM data is not used in un-latched form
The Emulator is therefore jumpered as:
- Latch ROM address on leading (falling) edge of CPR
- Disable ROM outputs (outputs logic zero) for duration of CPR
- Enable ROM outputs after CPR and for duration of machine cycle until next CPR
The resulting timing is shown below:
- Reading 0->1 The blue data trace transitions very rapidly after the end of CPR
- Reading 1->0 When the ROM outputs are disabled at the start of CPR, the level transition is passive, via pullup resistors. The wired backplane has significant capacitance and it takes 100nS or so for the level to exceed 2.4v but nevertheless a stable logic level is reached well before the second half of CPR, where the P2 reset pulse occurs.
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❯This suggests that an Emulator jumpered in this fashion should function correctly in a Wang 700.