Microcode Diagnostics - 1
The Core Diagnostics are conveniently packed into one ROM image, each can be started with one of the four hardware restart keys. These diagnostics increase in complexity and seek to test the most basic functions of the microcode engine.
PRIME: Single Instruction V-Register Count
This is a single microcode instruction, located at ROM address zero and coded to branch back to itself so as to create an infinite execution loop without needing any ROM address logic other than the ability to stay fixed at address zero. Microcode can have multiple effects programmed into a single instruction and this instruction also increments the V-Register to form an endless 4-bit count.
The logic analyzer is set up to monitor the ROM address and various other internal registers, including MAV (the V-Register):
Single instruction, count in V and read from RAM
Label > JADHI JAD MAV MAU MAT RB CA N0 PRIME
Base > Hex Hex Hex Hex Hex He He He Binar
____________ _____ ___ ___ ___ ___ __ __ __ _____
0 0 00 A F F F F 9 1
1 0 00 5 F F E E 4 0
2 0 00 6 F F 0 0 5 0
3 0 00 7 F F 1 1 6 0
4 0 00 8 F F 0 0 7 0
5 0 00 9 F F 1 1 8 0
6 0 00 A F F F F 9 0
7 0 00 B F F 1 1 A 0
8 0 00 C F F F F B 0
9 0 00 D F F 3 3 C 0
10 0 00 E F F 0 0 D 0
11 0 00 F F F 1 1 E 0
12 0 00 0 F F 2 2 F 0
13 0 00 1 F F 3 3 0 0
14 0 00 2 F F 2 2 1 0
15 0 00 3 F F F F 2 0
16 0 00 4 F F E E 3 0
17 0 00 5 F F E E 4 0
18 0 00 6 F F 0 0 5 0
19 0 00 7 F F 1 1 6 0
20 0 00 8 F F 0 0 7 0
21 0 00 9 F F 1 1 8 0
--- etc etc ---
Success:
- the ROM addresses in JADHI and JAD are zero and remain zero for each microcode cycle
- the MAV register shows an endless 4-bit count
- confirming the “add one” ALU function
- RB and CA (RAM data registers) correctly show the same value,
- value is the same for repeating RAM addresses in MAV, MAU, MAT
- all bits in the 4-bit RAM are able to take 0 or 1 values
- NO register correctly follows MAV, one cycle later
Full RAM Address Count, Conditional Execution
The next diagnostic code is seven microinstructions which zeros the MAV, MAU and MAT registers, counts these registes from 000 to FFF with carries propagating between registers and reads from RAM at the address pointed by the three registers together. The instructions are in the lowest part of ROM, requiring only the lower 4 bits of the ROM address to operate correctly.
Seven instruction MAV, MAu, MAT count and RAM read
Label > JADHI JAD MAV MAU MAT RB CA N0 PRIME
Base > Hex Hex Hex Hex Hex He He He Binar
____________ _____ ___ ___ ___ ___ __ __ __ _____
0 0 001 0 A 8 F F 0 1
1 0 001 0 A 8 F F 0 0
2 0 001 0 A 8 F F 0 0
3 0 006 0 0 8 F F 0 0
4 0 007 0 0 0 F F 0 0
5 0 008 0 0 0 F F 0 0
6 0 009 1 0 0 1 1 0 0
7 0 008 1 0 0 1 1 1 0
8 0 009 2 0 0 8 8 1 0
9 0 008 2 0 0 8 8 2 0
10 0 009 3 0 0 0 0 2 0
11 0 008 3 0 0 0 0 3 0
12 0 009 4 0 0 0 0 3 0
13 0 008 4 0 0 0 0 4 0
14 0 009 5 0 0 B B 4 0
15 0 008 5 0 0 B B 5 0
16 0 009 6 0 0 D D 5 0
17 0 008 6 0 0 D D 6 0
--- snip ---
4077 0 008 D 7 7 5 5 D 0
4078 0 009 E 7 7 D D D 0
4079 0 008 E 7 7 D D E 0
4080 0 009 F 7 7 5 5 E 0
4081 0 008 F 7 7 5 5 F 0
4082 0 009 0 7 7 F F F 0
4083 0 00A 0 8 7 F F 0 0
4084 0 00B 0 8 7 F F 0 0
4085 0 008 0 8 7 F F 0 0
4086 0 009 1 8 7 3 3 0 0
4087 0 008 1 8 7 3 3 1 0
4088 0 009 2 8 7 5 5 1 0
4089 0 008 2 8 7 5 5 2 0
4090 0 009 3 8 7 7 7 2 0
4091 0 008 3 8 7 7 7 3 0
Success:
- MAV, MAU, MAT are zeroed
- ALU can generate and store zeros in specified registers
- each register counts and carries propagate
- ALU add and carry flags function
- conditional branches on carry flags function
- ROM addresses are correctly set by microinstruction data
- RAM data and N0 registers correct as above
RAM Address Count with Call Stack and Upper ROM
This diagnostic is functionally the same as the address count above but is coded with two variations:
- the 2-level hardware call stack is used, calling and returning from low and high ROM addresses
- some code is placed in the highest part of ROM to test high ROM address bits
The code succeeds with listing very similar to above.
This verifies that the hardware call-return stack is working and that ROM addressing is working across all ROM address bits.
ROM address Walk
This diagnostic begins with a no-op microcode at ROM address 0x20 with its next-instruction address set to 0x40. Similar instructions are placed at addresses 0x40, 0x80, 0x100, 0x200, etc until 0x3FF when a next-instruction value of 0x20 causes the cycle to repeat.
ROM address walk
Label > JADHI JAD MAV MAU MAT RB CA N0 PRIME
Base > Hex Hex Hex Hex Hex He He He Binar
____________ _____ ___ ___ ___ ___ __ __ __ _____
0 2 03F 0 5 9 F F 0 1
1 0 003 0 5 9 F F 0 0
2 0 003 0 5 9 F F 0 0
3 0 020 0 5 9 F F 0 0
4 0 040 0 5 9 F F 0 0
5 0 080 0 5 9 F F 0 0
6 0 100 0 5 9 F F 0 0
7 1 000 0 5 9 F F 0 0
8 2 000 0 5 9 F F 0 0
9 2 001 0 5 9 F F 0 0
10 2 003 0 5 9 F F 0 0
11 2 007 0 5 9 F F 0 0
12 2 00F 0 5 9 F F 0 0
13 2 01F 0 5 9 F F 0 0
14 2 03F 0 5 9 F F 0 0
15 2 07F 0 5 9 F F 0 0
16 2 0FF 0 5 9 F F 0 0
17 2 1FF 0 5 9 F F 0 0
18 0 020 0 5 9 F F 0 0
19 0 040 0 5 9 F F 0 0
20 0 080 0 5 9 F F 0 0
This shows a successful walk through the ROM addresses, suggesting that all ROM address bits are functioning correctly.