Wang 600 Conditional Logic Fault
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Faulty Zero flag, traced to ROM emulator design flaw
The RAM test diagnostic microcode was failing with an error indication on the first address tested.
While this may suggest a RAM fault it must be recalled that the 600 display is generated by storing digit data in RAM before reading it out at a high enough rate to produce a ficker-free display. Since the machine is able to produce a good, stable display this suggests that at least some RAM addresses must be OK. Which leads to an alternative interpretation of the failed RAM test - that the execution engine logic is faulty, causing an erroneous error indication despite good RAM.
Test RAM Read with Custom Microcode
A 4-instruction loop was written and loaded into the emulator. This loop increments the three 4-bit registers that form the RAM address and then reads from the resulting 12-bit address. Machine CC2001 has 2K (of a possible 4K) RAM and the RAM address logic wraps the upper 2K back around over the lower 2K so that all addresses are usable, although addresses in the upper 2K will overwrite those in the lower 2K.
000: 0 + 0 ->[Zo,CC]; RESET; jump 001
001: 0 + 0 ->[Zo,CC]; CA = mem(T,U,V), CB = rom(T,U,V); jump 002
002: T = T + 0 + 1 ->[Zo,CC]; jump 003
003: U = U + 0 + 1 ->[Zo,CC]; jump 004
004: V = V + 0 + 1 ->[Zo,CC]; jump 001
Running this code while monitoring the RAM card with Logic Analyzer and oscilloscope showed:
- three RAM address registers (T, U, V) were all showing a correct 4-bit count
- RAM bank Chip Enable signals were correctly enabling the RAM for a 2K memory map
- RAM -12v power was switching correctly.
The designers of the 600 implemented a suggestion in the MK4008 RAM chip datasheet, switching the -12V supply off between RAM read, write or refresh cycles. The object was to reduce power dissipation in the memory bank but in a small, mains-powered RAM store this seems to be much added complexity for little added benefit. Perhaps the overheating problems of the Wang 700 were still in mind. In any case, the power switching logic was found to be OK, the oscilloscope traces showing:
- (yel) CK1 timing pulse, once per cycle
- (red) READ/!WRITE, with a burst of writes for RAM refresh
- (blu) RAM power control, high to supply power for write and read
- (grn) RAM power, power on when low at -12V It can be seen that RAM power is enabled for the duration of the burst of refresh cycles, and for a single RAM read cycle towards the end of the trace.
Test RAM Write-Read with Custom Microcode
The test above demonstrated RAM addressing, bank selection and RAM power, but not RAM writing. The custom microcode was extended to count the RAM address in sequence from zero, rippling through each higher-order RAM address register to form a 12-bit sequential binary count. The low order 4-bits were complemented and written to RAM, the RAM output register was cleared and the data read back and placed into the KA and KB registers (with the copy in KB incremented by 1). All of this could be achieved in 13 instructions:
000: [000000000 0000 01] 0 = 0 + 0; JMP 001
001: [001000000 0000 10] T = 0 + 0; JMP 002 // initialise T
002: [002000000 0000 11] U = 0 + 0; JMP 003 // initialise U
003: [003000000 0001 00] V = 0 + 0; JMP 004 // initialise V
004: [3166111F0 0001 10] CA = V xor F; RAM(T U V) = CA; JMP 006 // store V complement at T U V
005: [202110000 0003 04] U = U + 0 + 1; JMP 00C( :Z0) // V rollover, increment U
006: [006000000 0001 11] CA = 0 + 0; JMP 007 // zero CA before readback
007: [007700400 0002 00] CA = RAM(T U V); JMP 008 // read T U V back into CA
008: [604010000 0002 01] KA = CA + 0; JMP 009 // and store the readback in KA - tests KA also
009: [605110000 0002 10] KB = CA + 0 + 1; JMP 00A // store a different value to test KB
00A: [303110000 0001 04] V = V + 0 + 1; JMP 004( :Z0) // increment V, repeat main cycle unless V rollover
00B: [000000000 0000 00]
00C: [007000000 0001 00] Znoop = 0 + 0; JMP 004 // no U rollover, repeat main cycle
00D: [101110000 0001 00] T = T + 0 + 1; JMP 004 // U rollover, inc T and repeat main cycle
Monitoring the same signals as above, it was found that the V register (low-order) incremented through 16 values but the T and U registers remained zero. Since the ripple of counts betseen registers was achieved by a conditional jump when a lower-order register overflowed to zero, this suggested that the “zero” conditional logic may be broken.
Microcode Rewrite with Carry Flag
The RAM Write-Read microcode was rewritten to ripple the count when an increment operation generated a carry, rather than rolling over to zero.
In this case, the count proceeded as expected with ripple to higher order registers before finally rolling over to zero.
The execution engine is not handling conditional jumps on zero correctly. This may be the reason for the failed RAM test and must be corrected before further progress can be made.
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